The present disclosure relates to semiconductor integrated circuit devices, particularly relates to a configuration connecting an internal circuit, an electrode pad formed above a circuit block, and an ESD protection circuit which protects the internal circuit from damage due to electrostatic discharge (ESD).
In recent years, with higher integration of circuits, the number of pins of the semiconductor integrated circuit devices is increasing. To correspond to such an increase in the number of pins, a technique of arranging electrode pads in a matrix is suggested in, for example, Japanese Patent Publication No. H05-218204.
In general, an ESD protection circuit is positioned below an electrode pad. Thus, if many electrode pads are positioned above the circuit block, the ESD protection circuits may obstruct the circuit configuration in the circuit block, and this may result in problems, such as an increase in circuit area and high density of lines.
To solve the above problems, Japanese Patent Publication No. 2001-237317, for example, discloses a structure in which the ESD protection circuit is not positioned below the electrode pad, but is positioned at a periphery of a semiconductor integrated circuit device.